----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    12:03:33 04/22/2012 
-- Design Name: 
-- Module Name:    clock_generator - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity clock_generator is
	 generic (desiredFreq : positive range 1 to 5E6);
    Port ( clk_50MHz : in  STD_LOGIC;
           clk_out : out  STD_LOGIC);
end clock_generator;

architecture Behavioral of clock_generator is

	constant terminal_count : natural := 50E6/(2*desiredFreq);
	
	signal count : positive range 1 to terminal_count;
	
	signal clk_internal : std_logic := '0';
	
begin

	process(clk_50MHz)
		--variable clk_cnt: integer range 0 to 49999999:=1;
		begin
			if rising_edge(clk_50MHz) then
				if count = terminal_count then
					count <= 1;
					clk_internal <= not clk_internal;
				else
					count <= count + 1;
				end if;
			end if;
	end process;
	
	clk_out <= clk_internal;


end Behavioral;

